There is a growing worldwide interest in down-scaling basic electronic semiconductor devices to the nano range for meeting practical demands, such as power saving, building smaller integrated devices and obtaining optimum high speed. The tunneling field effect transistor (TFET), in particular, has received tremendous attention due to its potential to address power concerns in nano-electronics. This is attributed to the tunneling transmission process of electrons, i.e., a “cold” transmission process, rather than the thermionic process as in conventional MOSFET transistors. However, reducing the size of conventional CMOS electronic devices is limited by the depletion width of various doped (source and drain) terminals and the gate leakage current. Furthermore, the band to band tunneling limits the performance of such devices. The recent attempts of using an atomically thin graphene layer as transport channel are also encountering a problem from the absence of defined band structures which is not preferred in digital electronics.
In fact, the most recent improvement in device scaling has been announced by Intel for reaching the limit of 22 nm in the 3-D Tri-Gate Transistor Technology [1].